DS Tek - Nintendo DS Technical Information
This document contains both information of my own (c) neimod and information of GBATek (c) Martin Korth
Got any additions?
Send in anything related to DSTek to n.e.i.mod@h.ot.mai.l.com and remove the dots, except .com.

 

Index
DSTek Updates
Memory Map
System Control
LCD I/O Interrupts and Status
Computational Accelerators
Realtime Clock
Communication Ports
Serial Peripheral Interface
WRAM and VRAM Banks
DMA Transfers
Keypad Input
Interprocessor Communication
Sound
Timers
Interrupt Control


DSTek Updates

12 July - Added microphone, powermanagement to Serial Peripheral Interface.
12 July - Added sleep mode info, updated memory info.
13 July - Removed sndduty.png, added ASCII instead.
13 July - Added I/O addresses list for the engines when turning power on or off.
13 July - Added Computational Accelerators section.


Memory Map

ARM9 General Internal Memory
0000:0000-0000:7FFF    ITCM (32KBytes)
0200:0000-023F:FFFF    Main Memory (4MBytes)
037F:8000-037F:FFFF    Shared IWRAM (siwram) (32KBytes Max.)
0400:0000-0400:????    I/O RAM (??KBytes)
FFFF:0000-FFFF:7FFF    BIOS (32KBytes)
----RELOCATABLE----    DTCM (16KBytes)
----RELOCATABLE----    Instruction Cache (8KBytes)
----RELOCATABLE----    Data Cache (4KBytes)
--------N/A--------    Write Buffer (32Bytes x 16 FIFO)
ARM9 Internal Display Memory
0500:0000-0500:01FF    A-BG Palette RAM (512 Bytes)
0500:0200-0500:03FF    A-OBJ Palette RAM (512 Bytes)
0500:0400-0500:05FF    B-BG Palette RAM (512 Bytes)
0500:0600-0500:07FF    B-OBJ Palette RAM (512 Bytes)
0600:0000-0607:FFFF    A-BG VRAM (512KBytes Max.)
0620:0000-0621:FFFF    B-BG VRAM (128KBytes Max.)
0640:0000-0643:FFFF    A-OBJ VRAM (256KBytes Max.)
0660:0000-0661:FFFF    B-OBJ VRAM (128KBytes Max.)
0680:0000-068A:3FFF    LCD VRAM (656KBytes)
0700:0000-0700:03FF    A-OAM (1KBytes)
0700:0400-0700:07FF    B-OAM (1KBytes)
ARM9 External Memory (Game Pak)
0800:0000-09FF:FFFF    CART ROM (32MBytes)
0A00:0000-0A00:FFFF    CART RAM (64KBytes)

The ARM9's ICACHE and DCACHE can be used as fast RAM blocks (such as TCM), by locking them down to a specific memory range (See CP15 Cache Lockdown).
They can of course, be used as caches aswell.


ARM7 General Internal Memory
0000:0000-0000:3FFF    BIOS (16KBytes)
0200:0000-023F:FFFF    Main Memory (4MBytes)
037F:8000-037F:FFFF    Shared IWRAM (siwram) (32KBytes Max.)
0380:0000-0380:FFFF    Exclusive IWRAM (eiwram) (64KBytes)
0400:0000-0400:????    I/O RAM (??KBytes)
ARM7 Internal Display(=Work) Memory
0600:0000-0603:FFFF    WORK VRAM (256KBytes Max.)
ARM7 Wireless RAM
0480:0000-0480:7FFF    Wait State 0 WIRAM (32KBytes??)(maybe 8k??)
0480:8000-0480:FFFF    Wait State 1 WIRAM (32KBytes??)(maybe 8k??)
ARM7 External Memory (Game Pak)
0800:0000-09FF:FFFF    CART ROM (32MBytes)
0A00:0000-0A00:FFFF    CART RAM (64KBytes)

Memory mirroring
Every memory section, e.g. main memory, shared iwram, io, vram, palette, etc. are mirrored.
For example, Main Memory from 0200:0000-023F:FFFF is mirrored in 0240:0000-027F:FFFF, 0280:0000-02BF:FFFF, etc. until 02FF:FFFF
An other example, Shared IWRAM from 037F:8000-037F:FFFF, is mirrored from 0300:0000 to 037F:7FFF.
This is for each memory section, although it is sometimes difficult to tell where the mirroring starts and stops, ie. IO.

Shared IWRAM
The name shared IWRAM (consists of 2 16kb blocks) can be misleading, as only one CPU has access to it.
However, using WRAMCNT each 16k block can be assigned to a specific CPU.
When processing is done for example, the block can be assigned to the other CPU quickly for processing, without copying it via main memory or the IPC fifo.

Main Memory
Main memory, consisting of one big block of 4MB memory, can be accessed by both CPU's.
However, only one CPU can read/write/execute from it at a time. When both CPUs are trying to read main memory, one will have priority over the other.
See EXMEMCNT for more information.

System Control

0x04000204 - REG_EXMEMCNT - External Memory Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    RAM-region access cycle control   0..3=10,8,6,18 cycles  
9 2-3    ROM 1st access cycle control   0..3=10,8,6,18 cycles  
9 4    ROM 2nd access cycle control   0..1=6,4 cycles  
9 5-6    PHI-terminal output control   0..3=Lowlevel, 4.19MHz, 8.38MHZ, 16.76MHz clock output  
9 7    Cartridge access right   0=ARM9, 1=ARM7  
9 11    Card access right   0=ARM9, 1=ARM7  
9 14    Main Memory Interface mode   0=Asychronous (prohibited!), 1=Synchronous  
9 15    Main Memory priority   0=ARM9 priority, 1=ARM7 priority  


0x04000304 - REG_POWCNT - Power Control Register (R/W)
Cpu  Bit Name Expl.
7 0    Sound Speakers   0=Disable, 1=Enable  
7 1    Wifi   0=Disable, 1=Enable  

Cpu  Bit Name Expl.
9 0    LCD Screens   0=Disable, 1=Enable  
9 1    2D Engine A   0=Disable, 1=Enable  
9 2    3D Rendering Engine   0=Disable, 1=Enable  
9 3    3D Geometry Engine   0=Disable, 1=Enable  
9 9    2D Engine B   0=Disable, 1=Enable  
9 15    LCD Swap   0=Engine A Bottom, Engine B Top screen
1=Engine A Top, Engine B Bottom screen 		 

The following is a list of which I/O addresses are affected when power to specific engines is turned on or off:
2D Engine A:
04000008h - 0400004Dh, 04000050h - 04000055h, Engine A's OAM and palette RAM.
2D Engine B:
04001008h - 0400104Dh, 04001050h - 04001055h, Engine B's OAM and palette RAM.
Geometry Engine:
04000400h - 04000473h, 04000480h - 040004AFh, 040004C0h - 040004D3h, 04000500h - 04000507h, 04000540h - 04000543h, 04000580h - 04000483h, 040005C0h - 040005CBh, 04000600h - 04009607h, 04000610h - 04000611h, 04000620h - 04000635h, 04000640h - 040006A3h.
Rendering Engine:
04000320h - 04000321h 04000330h - 04000341h 04000350h - 0400035Dh 04000360h - 040003BFh.
Writing to the memory regions is invalid, and reading will return 0.
Writing to the register regions is invalid, but reading is read-enabled.

0x04000300 - REG_HALTCNT - Pause Control Register (R/W)
Cpu  Bit Name Expl.
9/7 0    Check   Purpose Unknown.  
9/7 14-15    Pause Mode   0..3=Halt, GBA Mode, Stop, Sleep  

Caution!
HALTCNT can only be accessed by BIOS functions, more specifically, SWI 0x1F(0000).

Sleep mode
Sleep mode can be entered by the ARM7 processor going into sleep mode (SWI 0x07(0000)).
The ARM9 processor does not seem to have a softwarematic feature to go into sleep mode, but will probably go into sleep mode when ARM7 is.

Caution!
LCD:
Before re-enabling the LCD after sleep mode, wait atleast 100ms before returning power to it.
Failing to do so might leave the powermanagement IC in an unrecoverable state.
When the LCD is turned off, the power supply to the sound amp is also turned off.
The speaker will then not function, but sound will come from the headphones, because the headphone amp is not effected.

Sound:
When restoring power to the sound circuit, wait atleast 15ms before playing any sounds on it.
Do not use the microphone for 500ms after power to the microphone is turned on.

Useful tip: A fully charged battery lasts 2 weeks with sleep-mode enabled.

Awaking from sleep mode
The DS can be waken up from either a timer irq, opening the screens irq, ds card or gba cartridge is removed irq, or when a certain key combination is pressed (with the exception of X and Y), also an irq.

LCD I/O Interrupts and Status

0x04000004 - REG_DISPSTAT - General LCD Status (R/W)
Cpu  Bit Name Expl.
9/7 0    V-Blank flag   0=Not in V-Blank, 1=in V-Blank  
9/7 1    H-Blank flag   0=Not in H-Blank, 1=in H-Blank  
9/7 2    V-Counter flag   0=No V-Counter Match, 1=V-Counter match  
9/7 3    V-Blank IRQ Enable   0=Disable, 1=Enable  
9/7 4    H-Blank IRQ Enable   0=Disable, 1=Enable  
9/7 5    V-Counter IRQ Enable   0=Disable, 1=Enable  
9/7 7-15    V-Counter Match   0..262  

Caution!
V-Counter Match represented as VC0..VC8, is stored as following in DISPSTAT:
[VC7][VC6][VC5][VC4][VC3][VC2][VC1][VC0][VC8]
The most significant bit of V-Counter Match is stored as the least significant bit.

0x04000006 - REG_VCOUNT - Vertical Counter (R)
Cpu  Bit Name Expl.
9/7 0-9    Current Scanline   0..262  

Unlike DISPSTAT, VCOUNT has the bits in the right order.

Computational Accelerators

The DS contains both divide and square root accelerators.

0x04000280 - REG_DIVCNT - Divide Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Division Mode   0..3=32bit/32bit, 64bit/32bit, 64bit/64bit, Prohibited.  
9 14    Division By Zero   0=No error, 1=Error  
9 15    Divider Status   0=Ready, 1=Busy  

Caution!
Wait until the busy flag is cleared before operating the divide or squareroot functions.
Calculation will be done when the busy flag changes to a ready state.

The divider numbers are in signed format, 1 sign bit, and 63 integer bits.

0x04000290 - REG_DIV_NUMER_L - Divide Numerator Lower Word (R/W)
0x04000294 - REG_DIV_NUMER_H - Divide Numerator Higher Word (R/W)
0x04000298 - REG_DIV_DENOM_L - Divide Denomerator Lower Word (R/W)
0x0400029C - REG_DIV_DENOM_H - Divide Denomerator Higher Word (R/W)
0x040002A0 - REG_DIV_RESULT_L - Divide Quotient (result) Lower Word (R/W)
0x040002A4 - REG_DIV_RESULT_H - Divide Quotient (result) Higher Word (R/W)
0x040002A8 - REG_DIV_REMAIN_L - Divide Remainder (result) Lower Word (R/W)
0x040002AC - REG_DIV_REMAIN_H - Divide Remainder (result) Higher Word (R/W)
Cpu  Bit Name Expl.
9 0-31    Number Data    

Caution!
All 64 bits of DIV_DENOM must be zero for the Division By Zero to function properly, even when diving by 32bits only.
When dividing by 32bits, clear the upper 32bits aswell, because if a previously signed denomerator was used, those bits will still be enabled.

1. Wait until busy flag is cleared.
2. Set the necessary registers.
3. Wait until busy flag is cleared.
4. Read back the result.

Division Calculation Cyclecount:
32bits/32bits: 18 cycles.
64bits/32bits: 34 cycles.
64bits/64bits: 34 cycles.

0x040002B0 - REG_SQRTCNT - Squareroot Control Register (R/W)
Cpu  Bit Name Expl.
9 0    Mode   0=32-bit input, 1=64-bit input  
9 15    Squareroot Calculator Status   0=Ready, 1=Busy  

The squareroot number is in unsigned format, 64 integer bits.
The result is always 32-bit unsigned.

0x040002B8 - REG_SQRT_PARAM_L - Squareroot Parameter Lower Word (R/W)
0x040002BC - REG_SQRT_PARAM_H - Squareroot Parameter Higher Word (R/W)
0x040002B4 - REG_SQRT_RESULT - Squareroot Result (R/W)
Cpu  Bit Name Expl.
9 0-31    Number Data    

Squareroot Calculation Cyclecount:
32bits: 13 cycles.
64bits: 13 cycles.

Realtime Clock

The DS has a built-in realtime clock.

0x04000138 - REG_RTCCNT - Realtime Clock Control Register (R/W)
Cpu  Bit Name Expl.
7 0    In/Out Data Bit   This is the Serial In/Out data bit as input or output.  
7 1    SCK Data Bit   This is the Serial CK data bit as input or output.  
7 2    CS Data Bit   This is the CS data bit as input or output.  
7 4    SIO Direction   0=Input, 1=Output  
7 5    SCK Direction   0=Input, 1=Output  
7 6    CS Direction   0=Input, 1=Output  


Communication Ports

The DS retains the same SIO registers from GBA, yet it has no communication port.

0x04000134 - REG_RCNT - General Purpose I/O Comm. Control Register (R/W)
Cpu  Bit Name Expl.
7 0    SC Data Bit   0=Low, 1=High  
7 1    SD Data Bit   0=Low, 1=High  
7 2    SI Data Bit   0=Low, 1=High  
7 3    SO Data Bit   0=Low, 1=High  
7 4    SC Direction Bit   0=Input 1=Output  
7 5    SD Direction Bit   0=Input 1=Output  
7 6    SI Direction Bit   0=Input 1=Output  
7 7    SO Direction Bit   0=Input 1=Output  
7 8    IRQ enable   0=Disable, 1=Enable  
7 14-15    Communication Mode   0=UART/Normal/Multi-Player, 1=Unused, 2=General Purpose Comm, 3=Joypad  

This section is 100% exactly the same as GBA, so for now visit GBATek if you want more information:
GBATek

Serial Peripheral Interface

0x040001C2 - REG_SPIDATA - SPI Data (R/W)
Cpu  Bit Name Expl.
7 0-15    Serial data   input/output  

0x040001C0 - REG_SPICNT - SPI Control Register (R/W)
Cpu  Bit Name Expl.
7 0-1    Baudrate   0..3=4MHz, 2MHz, 1MHz, 512kHz  
7 7    Busy flag   0=Ready, 1=Busy  
7 8-9    Device   0..3=Powermanagement, Firmware(NVRAM), Touchscreen/Microphone, Prohibited  
7 10    Clock mode   0=8 clocks, 1=16 clocks  
7 11    Transfer Mode   0=single byte, 1=continuous  
7 14    Interrupt Enable   0=Disabled, 1=Enable  
7 15    Enable   0=Disabled, 1=Enable  


Power management
The power management device, connected to the SPI bus, can control various peripherals.
To communicate with the power management device, use a baudrate of 1MHz and 8 clocks.
It controls the backlights for each LCD screen, the power LED, sound volume and control, the microphone amp and amp gain, and can also turn off the DS.
In addition, the battery status can also be retrieved.

PM 0H - REG_PM_CONTROL - Powermanagement Control (Register 0h) (R/W)
Cpu  Bit Name Expl.
7 0    Sound (Circuit) Power   0=Disable, 1=Enable  
7 1    Sound (Circuit?) Volume   0=Disable, 1=Enable  
7 2    Backlight Bottom LCD   0=Disable, 1=Enable  
7 3    Backlight Top LCD   0=Disable, 1=Enable  
7 4-5    Power LED Control   0..3=ON, ON, OFF(long) and ON(short), OFF(short) and ON(short)  
7 6    DS System Power   0=Enable, 1=Disable  

PM 1H - REG_PM_BATTERY - Battery Status (Register 1h) (R)
Cpu  Bit Name Expl.
7 0    Battery Status   0=Battery high, 1=Battery low  

PM 2H - REG_PM_AMP - Microphone Amplifier Control (Register 2h) (R/W)
Cpu  Bit Name Expl.
7 0    Amplifier   0=Disable, 1=Enable  

PM 3H - REG_PM_AMPGAIN - Microphone Amplifier Gain Control (Register 3h) (R/W)
Cpu  Bit Name Expl.
7 0-1    Gain   0..3=Gain 20, 40, 80, 160  

Reading and writing powermanagement registers
1. Wait until the SPI busy flag is cleared
2. Enable SPICNT, with baudrate 1MHz, powermanagement device, 8 clocks, and continuous mode.
3. Set SPIDATA to the register offset
   a)To read from the PM register, enable bit 7.
   b)To write to the PM register, clear bit 7.
4. Wait until the SPI busy flag is cleared
5. Set SPICNT to single byte mode now
6. a)Set SPIDATA to 0
   b)Set SPIDATA to the register value you want to write.
7. a)Wait until the SPI busy flag is cleared
8. a)the lower 8bits of SPIDATA now contain the contents of the PM register.

Touchscreen
The DS is equiped with a touchscreen, able to detect pressure and measure temperature.
To communicate with the touchscreen device, use a baudrate of 2MHz and 8 clocks.
Touchscreen command format:
[Start bit][A2][A1][A0][12/8 bit][SER/DFR][PD1][PD0]

Microphone
The DS contains a built-in microphone, and can be used for various purposes.
Microphone data actually comes from the touchscreen's AUX. (and not SPI device 3, incorrectly documented?)
The microphone data can be 12bits, or 8bits. Both are unsigned.

Caution!
Before reading microphone data, the microphone amplifier must be turned on.
See powermanagement for more information.

Reading microphone data
1. Wait until the SPI busy flag is cleared
2. Enable SPICNT, with baudrate 2MHz, touchscreen device, 8 clocks, and continuous mode.
3. Set SPIDATA to 0xEC (AUX enabled, 8bit mode, power-down between conversions, startbit).
   a) For 8bit mode, enable bit 3 (already enabled if 0xEC).
   b) For 12bit mode, clear bit 3.
4. Wait until the SPI busy flag is cleared
5. Set SPIDATA to 0x00.
6. Wait until the SPI busy flag is cleared
7. a) Bits 0-6 of SPIDATA now contain the upper 7 bits of audio data.
   b) Bits 0-6 of SPIDATA now contain the upper 7 bits of audio data.
8. Set SPICNT to single byte mode now
9. Set SPIDATA to 0x00
10.Wait until the SPI busy flag is cleared
11.a) Bit 7 of SPIDATA now contain the lowest bit of audio data.
   b) Bits 3-7 of SPIDATA now contain the lower 5 bits of audio data.
12.Combine both results to retrieve the complete audio data.
13.Flip the highest bit (7th or 11th) to convert the audio data to signed.

Reading microphone data must be done at a regular interval (ex. a timer at 16kHz) to get good audible audio.
Of course, it's possible to read microphone data at irregular intervals too.

WRAM and VRAM Banks

0x04000240 - REG_VRAMCNTA - VRAM-A Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Allocation Options   0=LCDC, 1=A-BG, 2=A-OBJ, 3=TEXIMG  
9 3-4    Offset   If LCDC, address range is always 0680:0000-0681:FFFF
If A-BG, OFS=0: address range is 0600:0000-0601:FFFF
If A-BG, OFS=1: address range is 0602:0000-0603:FFFF
If A-BG, OFS=2: address range is 0604:0000-0605:FFFF
If A-BG, OFS=3: address range is 0606:0000-0607:FFFF
If A-OBJ, OFS=0: address range is 0640:0000-0641:FFFF
If A-OBJ, OFS=1: address range is 0642:0000-0643:FFFF
If A-OBJ, OFS=2 and OFS=3 are prohibited
If TEXIMG, OFS=0: Texture image slot 0
If TEXIMG, OFS=1: Texture image slot 1
If TEXIMG, OFS=2: Texture image slot 2 (clear color image)
If TEXIMG, OFS=3: Texture image slot 3 (clear depth image)
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000241 - REG_VRAMCNTB - VRAM-B Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Allocation Options   0=LCDC, 1=A-BG, 2=A-OBJ, 3=TEXIMG  
9 3-4    Offset   See VRAM-A Control Register
If LCDC, address range is always 0682:0000-0683:FFFF
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000242 - REG_VRAMCNTC - VRAM-C Control Register (R/W)
Cpu  Bit Name Expl.
9 0-2    Allocation Options   0=LCDC, 1=A-BG, 2=ARM7, 3=TEXIMG, 4=B-BG, 5-7=Prohibited  
9 3-4    Offset   If LCDC, address range is always 0684:0000-0685:FFFF
If A-BG, OFS=0: address range is 0600:0000-0601:FFFF
If A-BG, OFS=1: address range is 0602:0000-0603:FFFF
If A-BG, OFS=2: address range is 0604:0000-0605:FFFF
If A-BG, OFS=3: address range is 0606:0000-0607:FFFF
If ARM7, OFS=0: address range is 0600:0000-0601:FFFF
If ARM7, OFS=1: address range is 0602:0000-0603:FFFF
If ARM7, OFS=2 and OFS=3 are prohibited
If TEXIMG, OFS=0: Texture image slot 0
If TEXIMG, OFS=1: Texture image slot 1
If TEXIMG, OFS=2: Texture image slot 2 (clear color image)
If TEXIMG, OFS=3: Texture image slot 3 (clear depth image)
If B-BG, address range is always 0620:0000-0621:FFFF
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000243 - REG_VRAMCNTD - VRAM-D Control Register (R/W)
Cpu  Bit Name Expl.
9 0-2    Allocation Options   0=LCDC, 1=A-BG, 2=ARM7, 3=TEXIMG, 4=B-BG, 5-7=Prohibited  
9 3-4    Offset   See VRAM-C Control Register.
If LCDC, address range is always 0686:0000-0687:FFFF
If B-BG, address range is always 0660:0000-0661:FFFF
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000244 - REG_VRAMCNTE - VRAM-E Control Register (R/W)
Cpu  Bit Name Expl.
9 0-2    Allocation Options   0=LCDC, 1=A-BG, 2=A-OBJ, 3=TEXPAL, 4=A-BGEXTPAL, 5-7=Prohibited  
9 3-4    Offset   If LCDC, address range is always 0688:0000-0688:FFFF
If A-BG, address range is always 0600:0000-0600:FFFF
If A-OBJ, address range is always 0640:0000-0640:FFFF
If TEXPAL, Texture palette slots 0-3
If A-BGEXTPAL, BG extended palette slots 0-3 (only the lower 32kB)
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000245 - REG_VRAMCNTF - VRAM-F Control Register (R/W)
Cpu  Bit Name Expl.
9 0-2    Allocation Options   0=LCDC, 1=A-BG, 2=A-OBJ, 3=TEXPAL, 4=A-BGEXTPAL, 5=A-OBJEXTPAL, 6-7=Prohibited  
9 3-4    Offset   If LCDC, address range is always 0689:0000-0693:FFFF
If A-BG, OFS=0: address range is 0600:0000-0600:3FFF
If A-BG, OFS=1: address range is 0600:4000-0607:FFFF
If A-BG, OFS=2: address range is 0601:0000-0601:3FFF
If A-BG, OFS=3: address range is 0601:4000-0601:7FFF
If A-OBJ, OFS=0: address range is 0600:0000-0600:3FFF
If A-OBJ, OFS=1: address range is 0600:4000-0600:7FFF
If A-OBJ, OFS=2: address range is 0601:0000-0601:3FFF
If A-OBJ, OFS=3: address range is 0601:4000-0601:7FFF
If TEXPAL, OFS=0: Texture palette slot 0
If TEXPAL, OFS=1: Texture palette slot 1
If TEXPAL, OFS=2: Texture palette slot 4
If TEXPAL, OFS=3: Texture palette slot 5
If A-BGEXTPAL, OFS=0: A-BG extended palette slots 0-1
If A-BGEXTPAL, OFS=1: A-BG extended palette slots 2-3
If A-BGEXTPAL, OFS=2 and OFS=3 are prohibited
If A-OBJEXTPAL, only lower 0-1 slots (2x4kB) are valid
 
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000246 - REG_VRAMCNTG - VRAM-G Control Register (R/W)
Cpu  Bit Name Expl.
9 0-2    Allocation Options   0=LCDC, 1=A-BG, 2=A-OBJ, 3=TEXPAL, 4=A-BGEXTPAL, 5=A-OBJEXTPAL, 6-7=Prohibited  
9 3-4    Offset   See VRAM-F Control Register
If LCDC, address range is always 0689:4000-0697:FFFF
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000248 - REG_VRAMCNTH - VRAM-H Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Allocation Options   0=LCDC, 1=B-BG, 2=B-BGEXTPAL, 3=Prohibited
If LCDC, address range is always 0689:8000-0689:FFFF
If B-BG, address range is always 0620:0000-0620:7FFF
If B-BGEXTPAL, BG extended palette slots 0-3
  
9 7    Enable   0=Disable bank, 1=Enable bank  

0x04000249 - REG_VRAMCNTI - VRAM-I Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Allocation Options   0=LCDC, 1=B-BG, 2=B-OBJ, 3=B-OBJEXTPAL
If LCDC, address range is always 068A:0000-068A:3FFF
If B-BG, address range is always 0620:8000-0620:BFFF
If B-OBJ, address range is always 0660:0000-0660:3FFF
If B-OBJEXTPAL, OBJ extended palette slots 0-1
  
9 7    Enable   0=Disable bank, 1=Enable bank  

Memory assigned to LCDC, ARM7, BG-VRAM and OBJ-VRAM banks are mapped to the ARM9 bus.
However, extended palette and texture slots (3D) are not mapped to the ARM9 bus.

0x04000247 - REG_WRAMCNT - (Shared) WRAM Control Register (R/W)
Cpu  Bit Name Expl.
9 0-1    Bank Specification   0=Bank0 and Bank1 to ARM9
1=Bank1 to ARM9, Bank0 to ARM7
2=Bank0 to ARM9, Bank1 to ARM7
3=Bank0 and Bank1 to ARM7 		 

Shared IWRAM consists of 2 16kB banks. Only one CPU can have access to a bank.
Initial WRAMCNT value is 3.

0x04000240 - REG_WVRAMSTAT - WVRAM Status Register (R/W)
Cpu  Bit Name Expl.
7 0    VRAM C Setting   0=Disabled, 1=Enabled ??  
7 1    VRAM D Setting   0=Disabled, 1=Enabled ??  
7 8    WRAM 0 Setting   0=Disabled, 1=Enabled ??  
7 9    WRAM 1 Setting   0=Disabled, 1=Enabled ??  

WVRAMSTAT is only for ARM7, and used to check if certain banks are available?

DMA Transfers

The DS includes four DMA channels, the highest priority is assigned to DMA0, followed by DMA1, DMA2, and DMA3.
DMA Channels with lower priority are paused until channels with higher priority have completed.
The DMA transfers are performed asynchronously from the CPU, however, when CPU is operating with DMA, RAM outside TCM or cache cannot be accessed.
Thus, CPU will effectively be paused with ARM7, but on ARM9 the program can continue to execute when it resides in TCM or cache.


0x040000B0 - REG_DMA0SAD - DMA 0 Source Address (W)
0x040000BC - REG_DMA1SAD - DMA 1 Source Address (W)
0x040000C8 - REG_DMA2SAD - DMA 2 Source Address (W)
0x040000D4 - REG_DMA3SAD - DMA 3 Source Address (W)
Cpu  Bit Name Expl.
9/7 0-31    DMA Source Address   Sets the DMA source address  


0x040000B4 - REG_DMA0DAD - DMA 0 Destination Address (W)
0x040000C0 - REG_DMA1DAD - DMA 1 Destination Address (W)
0x040000CC - REG_DMA2DAD - DMA 2 Destination Address (W)
0x040000D8 - REG_DMA3DAD - DMA 3 Destination Address (W)
Cpu  Bit Name Expl.
9/7 0-31    DMA Destination Address   Sets the DMA destination address  


0x040000B8 - REG_DMA0CNT - DMA 0 Control (R/W)
0x040000C4 - REG_DMA1CNT - DMA 1 Control (R/W)
0x040000D0 - REG_DMA2CNT - DMA 2 Control (R/W)
0x040000DC - REG_DMA3CNT - DMA 3 Control (R/W)
Cpu  Bit Name Expl.
7 0-15    Size Count   Sets the DMA data units to be transferred, in 16bit or 32bit units.  
7 21-22    Destination Address Control   0=Increment, 1=Decrement, 2=Fixed, 3=Increment/Reload  
7 23-24    Source Address Control   0=Increment, 1=Decrement, 2=Fixed, 3=Prohibited  
7 25    DMA Repeat   0=Off, 1=On  
7 26    DMA Transfer Type   0=16bit, 1=32bit  
7 28-29    DMA Start Timing   0=Immediately, 1=VBlank, 2=DS Card, 3=Special  
7 30    IRQ upon end of Size Count   0=Disable, 1=Enable  
7 31    DMA Enable   0=Off, 1=On  

The 'Special' timing depends on the DMA channel.
DMA channels 0 and 2: Wireless interrupt
DMA channels 1 and 3: Cartridge warning

Cpu  Bit Name Expl.
9 0-15    Size Count   Sets the DMA data units to be transferred, in 16bit or 32bit units.  
9 21-22    Destination Address Control   0=Increment, 1=Decrement, 2=Fixed, 3=Increment/Reload  
9 23-24    Source Address Control   0=Increment, 1=Decrement, 2=Fixed, 3=Prohibited  
9 25    DMA Repeat   0=Off, 1=On  
9 26    DMA Transfer Type   0=16bit, 1=32bit  
9 27-29    DMA Start Timing   0=Immediately, 1=VBlank, 2=HBlank, 3=HLine Start,
4=Main Mem Display, 5=DS Card, 6=Cartridge, 7=Geometry Fifo		  
9 30    IRQ upon end of Size Count   0=Disable, 1=Enable  
9 31    DMA Enable   0=Off, 1=On  

Notice the difference in DMA Timing between the ARM9 and ARM7.

Keypad Input

The DS has a built-in gamepad with 4 direction keys, and 8 buttons.

0x04000130 - REG_KEYINPUT - Key Status (R)
Cpu  Bit Name Expl.
9/7 0    Button A   0=Pressed, 1=Released.  
9/7 1    Button B   0=Pressed, 1=Released.  
9/7 2    Select   0=Pressed, 1=Released.  
9/7 3    Start   0=Pressed, 1=Released.  
9/7 4    Right   0=Pressed, 1=Released.  
9/7 5    Left   0=Pressed, 1=Released.  
9/7 6    Up   0=Pressed, 1=Released.  
9/7 7    Down   0=Pressed, 1=Released.  
9/7 8    Button R   0=Pressed, 1=Released.  
9/7 9    Button L   0=Pressed, 1=Released.  

It'd be usually recommended to read-out this register only once per frame, and to store the current state in memory.
As a side effect, this method avoids problems caused by switch bounce when a key is newly released or pressed.

0x04000132 - REG_KEYCNT - Key Interrupt Control (R/W)
Cpu  Bit Name Expl.
9/7 0    Button A   0=Ignore, 1=Select  
9/7 1    Button B   0=Ignore, 1=Select  
9/7 2    Select   0=Ignore, 1=Select  
9/7 3    Start   0=Ignore, 1=Select  
9/7 4    Right   0=Ignore, 1=Select  
9/7 5    Left   0=Ignore, 1=Select  
9/7 6    Up   0=Ignore, 1=Select  
9/7 7    Down   0=Ignore, 1=Select  
9/7 8    Button R   0=Ignore, 1=Select  
9/7 9    Button L   0=Ignore, 1=Select  
9/7 14    IRQ Enable   0=Disable, 1=Enable  
9/7 15    IRQ Condition   0=Logical OR, 1=Logical AND  

In logical OR mode, an interrupt is requested when ANY of the selected buttons is pressed.
In logical AND mode, an interrupt is requested when ALL of the selected buttons are pressed.

0x04000136 - REG_KEYXY - Key X/Y Input (R)
Cpu  Bit Name Expl.
7 0    Button X   0=pressed, 1=released  
7 1    Button Y   0=pressed, 1=released  
7 6    Touchpad   0=pressed, 1=released  
7 7    Screens status   0=Screens open, 1=folded  

Caution!
The touchpad bit will return the correct value when /PENIRQ has been set to enabled.
This can be enabled by sending a /PENIRQ enable command to the touchscreen via SPI.

Interprocessor Communication

The DS's ARM9 processor can communicate with the ARM7 processor by these I/O registers.

0x04000180 - REG_IPCSYNC - IPC Synchronize Register (R/W)
Cpu  Bit Name Expl.
9/7 0-3    IPC Remote Status   Reflects the remote processor's LOCALSTAT.  
9/7 8-11    IPC Local Status   Userconfigurable status for local processor.  
9/7 13    IPC IRQ Request   0=Nothing, 1=Trigger an interrupt on the remote processor  
9/7 14    IPC IRQ Enable   0=Disabled, 1=Allow remote processor to trigger IRQ  

The ARM7 can trigger an interrupt on the ARM9 (and vice versa) by writing a 1 to bit 13 of the ARM7's REG_IPCSYNC.
But, the ARM9 must allow this to happen by enabling bit 14 of ARM9's REG_IPCSYNC, and enable bit 16 of REG_IE.

The IPC Synchronize register is mostly used for sychronizing between the 2 CPU's.

example ARM9 code:
1. Setup shared ram banks to ARM7.
2. Copy data to shared ram.
3. Set bits 8-11 of IPCSYNC to a random value named x.
example ARM7 code:
1. Wait until lower 4bits of IPCSYNC to become value x.
2. Read data from shared ram.
3. Continue with program.

0x04100000 - REG_IPCFIFORECV - IPC Receive Fifo (R)
Cpu  Bit Name Expl.
9/7 0-31    Received Fifo Data   Fifo data received from the remote processor.  

0x04000188 - REG_IPCFIFOSEND - IPC Send Fifo (W)
Cpu  Bit Name Expl.
9/7 0-31    Sending Fifo Data   Fifo data ready for the remote processor to receive.  

Caution!
1. Do not read from the receive fifo when it is empty, or this will result in error.
2. Do not write to the send fifo when it is full, or this will result in error.

0x04000184 - REG_IPCFIFOCNT - IPC Fifo Control Register (R/W)
Cpu  Bit Name Expl.
9/7 0    Send Fifo Empty Status   0=Not Empty, 1=Empty  
9/7 1    Send Fifo Full Status   0=Not Full, 1=Full  
9/7 2    Send Fifo IRQ Enable   0=Disable, 1=IRQ on Send Fifo Empty  
9/7 3    Send Fifo Clear   0=Nothing, 1=Flush Send Fifo  
9/7 8    Receive Fifo Empty   0=Not Empty, 1=Empty  
9/7 9    Receive Fifo Full   0=Not Full, 1=Full  
9/7 10    Receive Fifo IRQ Enable   0=Disable, 1=IRQ on Receive Fifo Not Empty  
9/7 14    Error   0=No Error, 1=Error  
9/7 15    Enable Fifo   0=Disable, 1=Enable Receive & Send Fifo  

When writing to the send fifo, the data will be put in the fifo, until the remote processor has read it.
Thus, writing too much while the remote processor has not processed this data will result in send fifo overflow.

Sound

The DS contains 16 hardware sound channels.

Power control
Enable the DS speakers first in POWCNT; However this is not necessary when using headphones only.
When restoring power supply to the sound circuit, do not output any sound during the first 15 milliseconds.
When not using sound, turning power off to the sound circuit will reduce power consumption.

0x04000504 - REG_SOUNDBIAS - Sound Bias Register (R/W)
Cpu  Bit Name Expl.
7 0-15    Sound Bias   Undocumented  


0x04000500 - REG_SOUNDCNT - Sound Control Register (R/W)
Cpu  Bit Name Expl.
7 0-6    Master Volume   0..127=silent..loud  
7 8-9    Left Out   0..3=?  
7 10-11    Right Out   0..3=?  
7 12    Channel 1 ..?   Unknown  
7 13    Channel 3 ..?   Unknown  
7 15    Master Enable   0=Disable, 1=Enable  

0x04000400 - REG_SOUND0CNT - Sound Channel 0 Control Register (R/W)
0x04000410 - REG_SOUND1CNT - Sound Channel 1 Control Register (R/W)
0x04000420 - REG_SOUND2CNT - Sound Channel 2 Control Register (R/W)
0x04000430 - REG_SOUND3CNT - Sound Channel 3 Control Register (R/W)
0x04000440 - REG_SOUND4CNT - Sound Channel 4 Control Register (R/W)
0x04000450 - REG_SOUND5CNT - Sound Channel 5 Control Register (R/W)
0x04000460 - REG_SOUND6CNT - Sound Channel 6 Control Register (R/W)
0x04000470 - REG_SOUND7CNT - Sound Channel 7 Control Register (R/W)
0x04000480 - REG_SOUND8CNT - Sound Channel 8 Control Register (R/W)
0x04000490 - REG_SOUND9CNT - Sound Channel 9 Control Register (R/W)
0x040004A0 - REG_SOUND10CNT - Sound Channel 10 Control Register (R/W)
0x040004B0 - REG_SOUND11CNT - Sound Channel 11 Control Register (R/W)
0x040004C0 - REG_SOUND12CNT - Sound Channel 12 Control Register (R/W)
0x040004D0 - REG_SOUND13CNT - Sound Channel 13 Control Register (R/W)
0x040004E0 - REG_SOUND14CNT - Sound Channel 14 Control Register (R/W)
0x040004F0 - REG_SOUND15CNT - Sound Channel 15 Control Register (R/W)
Cpu  Bit Name Expl.
7 0-6    Volume   0..127=silent..loud  
7 8-9    Data Shift   0..3=None, 1bit, 2bit, 4bit  
7 15    Hold   0=Nothing, 1=Hold  
7 16-22    Panning   0..127=left..right  
7 24-26    Wave Duty   See below
  
7 27-28    Repeat Mode   0..3=Manual, Loop Infinite, One-Shot, Prohibited  
7 29-30    Format   0..3=PCM8, PCM16, IMA-ADPCM, PSG(Programmable Sound Generator)/(white)noise  
7 31    Channel Enable   0=Disable, 1=Enable  

Wave Duty:
000: 12.5% (__-_______-____)
001: 25.0% (_--______--____)
010: 37.5% (_---_____---___)
011: 50.0% (_----____----__)
100: 62.5% (-___-----___---)
101: 75.0% (-__------__----)
110: 87.5% (--_-------_----)
111: Prohibited
For PCM, the format is signed.

For IMA-ADPCM, the format is as following:
[7bit table index initial value][16bit initial value][4bit data][4bit data][4bit data][etc..]
When using ADPCM and loops, set the loopstart position to the data part, rather than the header.
Caution!
Do not change the ADPCM loop start position after playback. Stop playback first.

All channels support ADPCM/PCM, but only channels 8..13 can be used for PSG, and 14..15 for white noise.
The sampling frequency of the mixer is 1.04876 MHz with an amplitude resolution of 24 bits, but the sampling frequency after mixing with PWM modulation is 32.768 kHz with an amplitude resolution of 10 bits.

0x04000404 - REG_SOUND0SAD - Sound Channel 0 Data Source Register (W)
0x04000414 - REG_SOUND1SAD - Sound Channel 1 Data Source Register (W)
0x04000424 - REG_SOUND2SAD - Sound Channel 2 Data Source Register (W)
0x04000434 - REG_SOUND3SAD - Sound Channel 3 Data Source Register (W)
0x04000444 - REG_SOUND4SAD - Sound Channel 4 Data Source Register (W)
0x04000454 - REG_SOUND5SAD - Sound Channel 5 Data Source Register (W)
0x04000464 - REG_SOUND6SAD - Sound Channel 6 Data Source Register (W)
0x04000474 - REG_SOUND7SAD - Sound Channel 7 Data Source Register (W)
0x04000484 - REG_SOUND8SAD - Sound Channel 8 Data Source Register (W)
0x04000494 - REG_SOUND9SAD - Sound Channel 9 Data Source Register (W)
0x040004A4 - REG_SOUND10SAD - Sound Channel 10 Data Source Register (W)
0x040004B4 - REG_SOUND11SAD - Sound Channel 11 Data Source Register (W)
0x040004C4 - REG_SOUND12SAD - Sound Channel 12 Data Source Register (W)
0x040004D4 - REG_SOUND13SAD - Sound Channel 13 Data Source Register (W)
0x040004E4 - REG_SOUND14SAD - Sound Channel 14 Data Source Register (W)
0x040004F4 - REG_SOUND15SAD - Sound Channel 15 Data Source Register (W)
Cpu  Bit Name Expl.
7 0-26    Source Address   Pointer to the sound channel data  

0x04000408 - REG_SOUND0TMR - Sound Channel 0 Timer Register (W)
0x04000418 - REG_SOUND1TMR - Sound Channel 1 Timer Register (W)
0x04000428 - REG_SOUND2TMR - Sound Channel 2 Timer Register (W)
0x04000438 - REG_SOUND3TMR - Sound Channel 3 Timer Register (W)
0x04000448 - REG_SOUND4TMR - Sound Channel 4 Timer Register (W)
0x04000458 - REG_SOUND5TMR - Sound Channel 5 Timer Register (W)
0x04000468 - REG_SOUND6TMR - Sound Channel 6 Timer Register (W)
0x04000478 - REG_SOUND7TMR - Sound Channel 7 Timer Register (W)
0x04000488 - REG_SOUND8TMR - Sound Channel 8 Timer Register (W)
0x04000498 - REG_SOUND9TMR - Sound Channel 9 Timer Register (W)
0x040004A8 - REG_SOUND10TMR - Sound Channel 10 Timer Register (W)
0x040004B8 - REG_SOUND11TMR - Sound Channel 11 Timer Register (W)
0x040004C8 - REG_SOUND12TMR - Sound Channel 12 Timer Register (W)
0x040004D8 - REG_SOUND13TMR - Sound Channel 13 Timer Register (W)
0x040004E8 - REG_SOUND14TMR - Sound Channel 14 Timer Register (W)
0x040004F8 - REG_SOUND15TMR - Sound Channel 15 Timer Register (W)
Cpu  Bit Name Expl.
7 0-15    Timer Value   Sample frequency, timerval=-(16777216 / freq)  

Caution!
High sampling rates lead to more frequent DMA transfers, and will affect processor speed.

0x0400040C - REG_SOUND0LEN - Sound Channel 0 Looplength Register (W)
0x0400041C - REG_SOUND1LEN - Sound Channel 1 Looplength Register (W)
0x0400042C - REG_SOUND2LEN - Sound Channel 2 Looplength Register (W)
0x0400043C - REG_SOUND3LEN - Sound Channel 3 Looplength Register (W)
0x0400044C - REG_SOUND4LEN - Sound Channel 4 Looplength Register (W)
0x0400045C - REG_SOUND5LEN - Sound Channel 5 Looplength Register (W)
0x0400046C - REG_SOUND6LEN - Sound Channel 6 Looplength Register (W)
0x0400047C - REG_SOUND7LEN - Sound Channel 7 Looplength Register (W)
0x0400048C - REG_SOUND8LEN - Sound Channel 8 Looplength Register (W)
0x0400049C - REG_SOUND9LEN - Sound Channel 9 Looplength Register (W)
0x040004AC - REG_SOUND10LEN - Sound Channel 10 Looplength Register (W)
0x040004BC - REG_SOUND11LEN - Sound Channel 11 Looplength Register (W)
0x040004CC - REG_SOUND12LEN - Sound Channel 12 Looplength Register (W)
0x040004DC - REG_SOUND13LEN - Sound Channel 13 Looplength Register (W)
0x040004EC - REG_SOUND14LEN - Sound Channel 14 Looplength Register (W)
0x040004FC - REG_SOUND15LEN - Sound Channel 15 Looplength Register (W)
Cpu  Bit Name Expl.
7 0-21    Loop Length   Sample loop length  

0x0400040A - REG_SOUND0PNT - Sound Channel 0 Loopstart Register (W)
0x0400041A - REG_SOUND1PNT - Sound Channel 1 Loopstart Register (W)
0x0400042A - REG_SOUND2PNT - Sound Channel 2 Loopstart Register (W)
0x0400043A - REG_SOUND3PNT - Sound Channel 3 Loopstart Register (W)
0x0400044A - REG_SOUND4PNT - Sound Channel 4 Loopstart Register (W)
0x0400045A - REG_SOUND5PNT - Sound Channel 5 Loopstart Register (W)
0x0400046A - REG_SOUND6PNT - Sound Channel 6 Loopstart Register (W)
0x0400047A - REG_SOUND7PNT - Sound Channel 7 Loopstart Register (W)
0x0400048A - REG_SOUND8PNT - Sound Channel 8 Loopstart Register (W)
0x0400049A - REG_SOUND9PNT - Sound Channel 9 Loopstart Register (W)
0x040004AA - REG_SOUND10PNT - Sound Channel 10 Loopstart Register (W)
0x040004BA - REG_SOUND11PNT - Sound Channel 11 Loopstart Register (W)
0x040004CA - REG_SOUND12PNT - Sound Channel 12 Loopstart Register (W)
0x040004DA - REG_SOUND13PNT - Sound Channel 13 Loopstart Register (W)
0x040004EA - REG_SOUND14PNT - Sound Channel 14 Loopstart Register (W)
0x040004FA - REG_SOUND15PNT - Sound Channel 15 Loopstart Register (W)
Cpu  Bit Name Expl.
7 0-15    Loop Start   Sample loop start position  


Sound Capture
The DS contains 2 built-in sound capture devices that can capture output waveform data to memory.
Sound capture 0 can capture output from left-mixer or output from channel 0.
Sound capture 1 can capture output from right-mixer or output from channel 2.
The sampling frequency can be set up to 1.04876 MHz. The amplitude resolution can also be set from 8 bits to 16 bits.

0x04000508 - REG_SNDCAPCNT - Sound Capture Control Register (R/W)
Cpu  Bit Name Expl.
7 0    Capture 0 Out   Unknown  
7 1    Capture 0 In   Unknown  
7 2    Capture 0 Repeat   Unknown  
7 3    Capture 0 Format   Unknown  
7 7    Capture 0 Enable   0=Disable, 1=Enable  
7 8    Capture 1 Out   Unknown  
7 9    Capture 1 In   Unknown  
7 10    Capture 1 Repeat   Unknown  
7 11    Capture 1 Format   Unknown  
7 15    Capture 1 Enable   0=Disable, 1=Enable  

0x04000510 - REG_SNDCAP0DAD - Sound Capture 0 Destination Address (W)
0x04000518 - REG_SNDCAP1DAD - Sound Capture 1 Destination Address (W)
Cpu  Bit Name Expl.
7 0-26    Destination address   Pointer to buffer for captured audio  

0x04000514 - REG_SNDCAP0LEN - Sound Capture 0 Length (R/W)
0x0400051C - REG_SNDCAP1LEN - Sound Capture 1 Length (R/W)
Cpu  Bit Name Expl.
7 0-15    Length   Buffer length  


Timers

The DS includes eight incrementing 16bit timers, four for each CPU.

0x04000100 - REG_TM0CNT_L - Timer 0 Counter/Reload (R/W)
0x04000104 - REG_TM1CNT_L - Timer 1 Counter/Reload (R/W)
0x04000108 - REG_TM2CNT_L - Timer 2 Counter/Reload (R/W)
0x0400010C - REG_TM3CNT_L - Timer 3 Counter/Reload (R/W)
Cpu  Bit Name Expl.
9/7 0-15    Timer Reload/Counter   Sets the reload value, reading gives current counter value  

Writing to these registers intializes the <reload> value (but does not directly affect the current counter value). Reading returns the current <counter> value (or the recent/frozen counter value if the timer has been stopped).
The reload value is copied into the counter only upon following two situations: Automatically upon timer overflows, or when the timer start bit becomes changed from 0 to 1.
Note: When simultaneously changing the start bit from 0 to 1, and setting the reload value at the same time (by a single 32bit I/O operation), then the newly written reload value is recognized as new counter value.

0x04000102 - REG_TM0CNT_H - Timer 0 Control (R/W)
0x04000106 - REG_TM1CNT_H - Timer 1 Control (R/W)
0x0400010A - REG_TM2CNT_H - Timer 2 Control (R/W)
0x0400010E - REG_TM3CNT_H - Timer 3 Control (R/W)
Cpu  Bit Name Expl.
9/7 0-1    Prescalar Selection   0=F/1, 1=F/64, 2=F/256, 3=F/1024  
9/7 2    Count-up Timing   0=Normal, 1=See below  
9/7 6    Timer IRQ Enable   0=Disable, 1=IRQ on Timer overflow  
9/7 9    Timer Start/Stop   0=Stop, 1=Operate  
9/7 7    Timer Start/Stop   0=Stop, 1=Operate  

When Count-up Timing is enabled, the prescaler value is ignored, instead the time is incremented each time when the previous counter overflows. This function cannot be used for Timer 0 (as it is the first timer).
F = System Clock (33.514MHz = 225MHz).

Interrupt Control

0x04000208 - REG_IME - Interrupt Master Enable Register (R/W)
Cpu  Bit Name Expl.
9/7 0    Disable all interrupts   0=Disable all, 1=See IE register  

Note that there is another 'master enable flag' directly in the CPUs Status Register (CPSR) accessable in privileged modes.
0x04000210 - REG_IE - Interrupt Enable Register (R/W)
0x04000214 - REG_IF - Interrupt Request Flags / IRQ Acknowledge (R/W)
Cpu  Bit Name Expl.
7 0    LCD V-Blank   0=Disable, 1=Enable  
7 1    LCD H-Blank   0=Disable, 1=Enable  
7 2    LCD V-Counter Match   0=Disable, 1=Enable  
7 3    Timer 0 Overflow   0=Disable, 1=Enable  
7 4    Timer 1 Overflow   0=Disable, 1=Enable  
7 5    Timer 2 Overflow   0=Disable, 1=Enable  
7 6    Timer 3 Overflow   0=Disable, 1=Enable  
7 8    DMA 0   0=Disable, 1=Enable  
7 9    DMA 1   0=Disable, 1=Enable  
7 10    DMA 2   0=Disable, 1=Enable  
7 11    DMA 3   0=Disable, 1=Enable  
7 12    Keypad   0=Disable, 1=Enable  
7 13    Gamepak Cartridge   0=Disable, 1=Enable  
7 16    ARM 9 IPC   0=Disable, 1=Enable  
7 17    IPC Send Fifo Empty   0=Disable, 1=Enable  
7 18    IPC Recv Fifo Not Empty   0=Disable, 1=Enable  
7 19    Card Data   0=Disable, 1=Enable  
7 20    Card   0=Disable, 1=Enable  
7 22    Screens unfolding   0=Disable, 1=Enable  
7 23    SPI   0=Disable, 1=Enable  
7 24    Wifi   0=Disable, 1=Enable  

Cpu  Bit Name Expl.
9 0    LCD V-Blank   0=Disable, 1=Enable  
9 1    LCD H-Blank   0=Disable, 1=Enable  
9 2    LCD V-Counter Match   0=Disable, 1=Enable  
9 3    Timer 0 Overflow   0=Disable, 1=Enable  
9 4    Timer 1 Overflow   0=Disable, 1=Enable  
9 5    Timer 2 Overflow   0=Disable, 1=Enable  
9 6    Timer 3 Overflow   0=Disable, 1=Enable  
9 8    DMA 0   0=Disable, 1=Enable  
9 9    DMA 1   0=Disable, 1=Enable  
9 10    DMA 2   0=Disable, 1=Enable  
9 11    DMA 3   0=Disable, 1=Enable  
9 12    Keypad   0=Disable, 1=Enable  
9 13    Gamepak Cartridge   0=Disable, 1=Enable  
9 16    ARM 7 IPC   0=Disable, 1=Enable  
9 17    IPC Send Fifo Empty   0=Disable, 1=Enable  
9 18    IPC Recv Fifo Not Empty   0=Disable, 1=Enable  
9 19    Card Data   0=Disable, 1=Enable  
9 20    Card   0=Disable, 1=Enable  
9 21    Geometry Engine Fifo   0=Disable, 1=Enable  

Interrupts must be manually enabled by IE, and in the user interrupt handler acknowledged by writing a "1" to one of the IF's IRQ bits, the IRQ bit will then be cleared.

Caution!
A corresponding interrupt could occur even while a command to clear IME or each flag of the IE register is being executed. When clearing a flag of IE, you need to clear IME in advance so that mismatching of interrupt checks will not occur.

BIOS Interrupt handling
Upon interrupt execution, the CPU is switched into IRQ mode, and the physical interrupt vector is called.
For ARM7, this vector is in the BIOS, which is located at 0x00000000.
For ARM9, this vector is also in the BIOS by default, located at 0xFFFF0000
However, the CP15 of the ARM9 can be changed, so that this vector for ARM9 is located at 0x00000000 aswell (but not the same BIOS as ARM7).
The vector for ARM7 will jump to the ARM-code user irq handler at 0x0380FFFC, the vector for ARM9 will jump to the location of DTCM+0x3FFC.

DTCM+0x3FFC - REG_IRQHANDLER - Interrupt Handler Address (R/W)
Cpu  Bit Name Expl.
9 0-31    Interrupt Handler Address   Pointer to the user interrupt handler.  

0x0380FFFC - REG_IRQHANDLER - Interrupt Handler Address (R/W)
Cpu  Bit Name Expl.
7 0-31    Interrupt Handler Address   Pointer to the user interrupt handler.  

DTCM+0x3FF8 - REG_IRQCHECK - Interrupt Check Flag (R/W)
0x0380FFF8 - REG_IRQCHECK - Interrupt Check Flag (R/W)
REG_IRQCHECK is used by the BIOS functions WaitIntr and VBlankIntrWait, it is a pre-allocated space used by the BIOS.
If you wish to make use of these BIOS functions (and you should as it's the only way to wait with low power consumption), the user interrupt handler must do the following:

REG_IRQCHECK = REG_IRQCHECK | (REG_IE & REG_IF)
As you can see, REG_IRQCHECK is orred with the currently processed interrupt flag.


I/O Overview
ARM9 I/O Registers
0x04000004 REG_DISPSTAT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VCNT
  
VCNT IRQ
HBL IRQ
VBL IRQ
VCNT
HBL
VBL
0x04000006 REG_VCOUNT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
SCANLINE
0x040000B0 REG_DMA0SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000B4 REG_DMA0DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000B8 REG_DMA0CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000BC REG_DMA1SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000C0 REG_DMA1DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000C4 REG_DMA1CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000C8 REG_DMA2SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000CC REG_DMA2DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000D0 REG_DMA2CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000D4 REG_DMA3SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000D8 REG_DMA3DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000DC REG_DMA3CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x04000100 REG_TM0CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x04000102 REG_TM0CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000104 REG_TM1CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x04000106 REG_TM1CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000108 REG_TM2CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x0400010A REG_TM2CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x0400010C REG_TM3CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x0400010E REG_TM3CNT_H (R/W)
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000130 REG_KEYINPUT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
L
R
DOWN
UP
LEFT
RIGHT
START
SELECT
B
A
0x04000132 REG_KEYCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOGIC
IRQ
        
L
R
DOWN
UP
LEFT
RIGHT
START
SELECT
B
A
0x04000180 REG_IPCSYNC (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
 
IRQ
IREQ
  
LOCALSTAT
        
REMOTESTAT
0x04000184 REG_IPCFIFOCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
ERROR
      
RECV_IRQ
RECV_FULL
RECV_EMPTY
        
SEND_CLEAR
SEND_IRQ
SEND_FULL
SEND_EMPTY
0x04000188 REG_IPCFIFOSEND (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO DATA
0x04000204 REG_EXMEMCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP
IFM
    
CARD
      
CART
PHI
ROM2nd
ROM1st
RAM
0x04000208 REG_IME (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                                                             
ENABLE
0x04000210 REG_IE (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
GX
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
0x04000214 REG_IF (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
GX
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
0x04000240 REG_VRAMCNTA (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
  
MST
0x04000241 REG_VRAMCNTB (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
  
MST
0x04000242 REG_VRAMCNTC (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
MST
0x04000243 REG_VRAMCNTD (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
MST
0x04000244 REG_VRAMCNTE (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
MST
0x04000245 REG_VRAMCNTF (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
MST
0x04000246 REG_VRAMCNTG (R/W)
7
6
5
4
3
2
1
0
ENABLE
    
OFS
MST
0x04000247 REG_WRAMCNT (R/W)
7
6
5
4
3
2
1
0
           
BANKCONFIG
0x04000248 REG_VRAMCNTH (R/W)
7
6
5
4
3
2
1
0
ENABLE
          
MST
0x04000249 REG_VRAMCNTI (R/W)
7
6
5
4
3
2
1
0
ENABLE
          
MST
0x04000280 REG_DIVCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUSY
DIVZERO
                        
MODE
0x04000290 REG_DIV_NUMER_L (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x04000294 REG_DIV_NUMER_H (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x04000298 REG_DIV_DENOM_L (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x0400029C REG_DIV_DENOM_H (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002A0 REG_DIV_RESULT_L (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002A4 REG_DIV_RESULT_H (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002A8 REG_DIV_REMAIN_L (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002AC REG_DIV_REMAIN_H (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002B0 REG_SQRTCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUSY
                            
MODE
0x040002B4 REG_SQRT_RESULT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002B8 REG_SQRT_PARAM_L (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x040002BC REG_SQRT_PARAM_H (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUMBER
0x04000300 REG_HALTCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
                          
CHK
0x04000304 REG_POWCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCDSWAP
          
2D-B
          
GEOMETRY
RENDER
2D-A
LCD
0x04100000 REG_IPCFIFORECV (R)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO DATA
DTCM+0x3FF8 REG_IRQCHECK (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
GX
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
DTCM+0x3FFC REG_IRQHANDLER (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDRESS
ARM7 I/O Registers
0x0380FFF8 REG_IRQCHECK (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
             
WIFI
SPI
SCREENS
  
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
0x0380FFFC REG_IRQHANDLER (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDRESS
0x04000004 REG_DISPSTAT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VCNT
  
VCNT IRQ
HBL IRQ
VBL IRQ
VCNT
HBL
VBL
0x04000006 REG_VCOUNT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
SCANLINE
0x040000B0 REG_DMA0SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000B4 REG_DMA0DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000B8 REG_DMA0CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
  
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000BC REG_DMA1SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000C0 REG_DMA1DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000C4 REG_DMA1CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
  
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000C8 REG_DMA2SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000CC REG_DMA2DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000D0 REG_DMA2CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
  
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x040000D4 REG_DMA3SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOURCE
0x040000D8 REG_DMA3DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESTINATION
0x040000DC REG_DMA3CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
TIMING
  
TYPE
REPEAT
SRC CONTROL
DST CONTROL
          
LENGTH
0x04000100 REG_TM0CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x04000102 REG_TM0CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000104 REG_TM1CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x04000106 REG_TM1CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000108 REG_TM2CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x0400010A REG_TM2CNT_H (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x0400010C REG_TM3CNT_L (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD/COUNTER
0x0400010E REG_TM3CNT_H (R/W)
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                           
ENABLE
  
ENABLE
IRQ
      
COUNTUP
PRESCALER
0x04000130 REG_KEYINPUT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
L
R
DOWN
UP
LEFT
RIGHT
START
SELECT
B
A
0x04000132 REG_KEYCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOGIC
IRQ
        
L
R
DOWN
UP
LEFT
RIGHT
START
SELECT
B
A
0x04000134 REG_RCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
          
IRQ
SO DIR
SI DIR
SD DIR
SC DIR
SO DATA
SI DATA
SD DATA
SC DATA
0x04000136 REG_KEYXY (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
               
FOLDED
TOUCH
        
PADY
PADX
0x04000138 REG_RTCCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                 
CS DIRECTION
SCK DIRECTION
SIO DIRECTION
  
CS DATA
SCK DATA
SIO DATA
0x04000180 REG_IPCSYNC (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
 
IRQ
IREQ
  
LOCALSTAT
        
REMOTESTAT
0x04000184 REG_IPCFIFOCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
ERROR
      
RECV_IRQ
RECV_FULL
RECV_EMPTY
        
SEND_CLEAR
SEND_IRQ
SEND_FULL
SEND_EMPTY
0x04000188 REG_IPCFIFOSEND (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO DATA
0x040001C0 REG_SPICNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
IRQ
    
MODE
CLOCKS
DEVICE
BUSY
          
BAUDRATE
0x040001C2 REG_SPIDATA (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA
0x04000208 REG_IME (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                                                             
ENABLE
0x04000210 REG_IE (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
             
WIFI
SPI
SCREENS
  
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
0x04000214 REG_IF (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
             
WIFI
SPI
SCREENS
  
CARD
CARDDATA
IPCRECV
IPCSEND
ARM9
    
CART
KEY
DMA3
DMA2
DMA1
DMA0
  
TM3
TM2
TM1
TM0
VCNT
HBL
VBL
0x04000240 REG_WVRAMSTAT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
           
WRAM 1
WRAM 0
            
VRAM D
VRAM C
0x04000300 REG_HALTCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
                          
CHK
0x04000304 REG_POWCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                           
WIFI
SPEAKERS
0x04000400 REG_SOUND0CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000404 REG_SOUND0SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000408 REG_SOUND0TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400040A REG_SOUND0PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400040C REG_SOUND0LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000410 REG_SOUND1CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000414 REG_SOUND1SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000418 REG_SOUND1TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400041A REG_SOUND1PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400041C REG_SOUND1LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000420 REG_SOUND2CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000424 REG_SOUND2SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000428 REG_SOUND2TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400042A REG_SOUND2PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400042C REG_SOUND2LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000430 REG_SOUND3CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000434 REG_SOUND3SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000438 REG_SOUND3TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400043A REG_SOUND3PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400043C REG_SOUND3LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000440 REG_SOUND4CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000444 REG_SOUND4SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000448 REG_SOUND4TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400044A REG_SOUND4PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400044C REG_SOUND4LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000450 REG_SOUND5CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000454 REG_SOUND5SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000458 REG_SOUND5TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400045A REG_SOUND5PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400045C REG_SOUND5LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000460 REG_SOUND6CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000464 REG_SOUND6SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000468 REG_SOUND6TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400046A REG_SOUND6PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400046C REG_SOUND6LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000470 REG_SOUND7CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000474 REG_SOUND7SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000478 REG_SOUND7TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400047A REG_SOUND7PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400047C REG_SOUND7LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000480 REG_SOUND8CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000484 REG_SOUND8SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000488 REG_SOUND8TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400048A REG_SOUND8PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400048C REG_SOUND8LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000490 REG_SOUND9CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x04000494 REG_SOUND9SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x04000498 REG_SOUND9TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x0400049A REG_SOUND9PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x0400049C REG_SOUND9LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004A0 REG_SOUND10CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004A4 REG_SOUND10SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004A8 REG_SOUND10TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004AA REG_SOUND10PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004AC REG_SOUND10LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004B0 REG_SOUND11CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004B4 REG_SOUND11SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004B8 REG_SOUND11TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004BA REG_SOUND11PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004BC REG_SOUND11LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004C0 REG_SOUND12CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004C4 REG_SOUND12SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004C8 REG_SOUND12TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004CA REG_SOUND12PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004CC REG_SOUND12LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004D0 REG_SOUND13CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004D4 REG_SOUND13SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004D8 REG_SOUND13TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004DA REG_SOUND13PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004DC REG_SOUND13LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004E0 REG_SOUND14CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004E4 REG_SOUND14SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004E8 REG_SOUND14TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004EA REG_SOUND14PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004EC REG_SOUND14LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x040004F0 REG_SOUND15CNT (R/W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
FORMAT
REPEAT
DUTY
  
PAN
HOLD
          
SHIFT
  
VOL
0x040004F4 REG_SOUND15SAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
SRC ADDRESS
0x040004F8 REG_SOUND15TMR (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMER
0x040004FA REG_SOUND15PNT (W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PNT
0x040004FC REG_SOUND15LEN (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
                   
LEN
0x04000500 REG_SOUNDCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
  
CH3
CH1
ROUT
LOUT
  
VOL
0x04000504 REG_SOUNDBIAS (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIAS
0x04000508 REG_SNDCAPCNT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAP1ENABLE
      
CAP1FMT
CAP1REPEAT
CAP1IN
CAP1OUT
CAP0ENABLE
      
CAP0FMT
CAP0REPEAT
CAP0IN
CAP0OUT
0x04000510 REG_SNDCAP0DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
DST ADDRESS
0x04000514 REG_SNDCAP0LEN (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LENGTH
0x04000518 REG_SNDCAP1DAD (W)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
         
DST ADDRESS
0x0400051C REG_SNDCAP1LEN (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LENGTH
0x04100000 REG_IPCFIFORECV (R)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO DATA
PM 0H REG_PM_CONTROL (R/W)
7
6
5
4
3
2
1
0
 
POWER
LED
BKLT_TOP
BKLT_BOTTOM
SND_VOL
SND_PWR
PM 1H REG_PM_BATTERY (R)
7
6
5
4
3
2
1
0
             
BATTERY
PM 2H REG_PM_AMP (R/W)
7
6
5
4
3
2
1
0
             
AMP
PM 3H REG_PM_AMPGAIN (R/W)
7
6
5
4
3
2
1
0
           
GAIN